Gap-filling of O3 -TEOS for shallow trench isolation

ABSTRACT

An improved method of gap filling shallow trench isolation with ozone-TEOS is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate. A thermal oxide layer is grown within the isolation trenches. A plasma enhanced SiH 4  oxide layer is deposited over the nitride layer and over the thermal oxide layer within the isolation trenches and treated with N 2  plasma. Thereafter, an ozone-TEOS layer is deposited overlying the plasma enhanced SiH 4  oxide layer and filling the isolation trenches. The ozone-TEOS layer and the plasma enhanced SiH 4  oxide layer are polished away stopping at the nitride layer. This completes the formation of shallow trench isolation in the fabrication of the integrated circuit device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the fabrication of integrated circuitdevices, and more particularly, to a method of improving the gap fillingcharacteristics of an ozone-TEOS shallow trench isolation layer in thefabrication of integrated circuits.

2. Description of the Prior Art

Shallow trench isolation (STI) has been gaining popularity forquarter-micron technology and beyond to replace the traditional localoxidation of silicon (LOCOS) isolation process. However, as the designrule continues to shrink, gap filling of the smaller trench becomes agreat challenge. Currently, both ozone-TEOS (tetraethoxysilane) and highdensity plasma chemical vapor deposited (HDPCVD) oxide are being studiedextensively for STI gap filling. For the O₃ -TEOS approach, surfacesensitivity of subatmospheric chemical vapor deposited (SACVD) O₃ -TEOSoxide on thermal oxide is the most critical issue. An underlayer ofthermal oxide is desired for good sidewall isolation. However, thesurface sensitivity of O₃ -TEOS deposition over thermal oxide results ina degradation of the O₃ -TEOS deposition rate and wet etch rate. Thisproblem is discussed in the paper, "Surface Related Phenomena inIntegrated PECVD/Ozone-TEOS SACVD Processes for Sub-Half Micron GapFill: Electrostatic Effects," by K. Kwok et al, J. Electrochem. Soc.,Vol. 141, No. 8, August 1994. Traditional methods to eliminate surfacesensitivity include the use of Ar or N₂ plasma treatment on theunderlayer and power ramp-down deposition of a PE-TEOS (plasma-enhanced)underlayer. However, we have found that these methods do not provide anacceptable solution because of severe surface porosity of theseunderlayers.

U.S. Pat. No. 5,536,681 to Jang et al teaches a method to improve thegap-filling capability of ozone-TEOS over metal lines by selectivelytreating with N₂ plasma portions of an underlayer overlying the metallines. This selective treatment leads to differing deposition rates onthe top of the metal lines and on the bottom and sidewalls of the gapsto improve the gap filling characteristics of the ozone-TEOS. U.S. Pat.No. 5,518,959 to Jang et al teaches a method of selectively depositingan oxide layer using a PE-OX layer with a selectively deposited O₃ -TEOSlayer. U.S. Pat. No. 5,459,108 to Doi et al teaches a method of formingan oxide layer using O₃ -TEOS with N₂ added to the deposition gases inorder to decrease the moisture content of the resulting film. The paperof Kwok et al, cited above, discusses using an N₂ plasma treatment of aPE-TEOS underlayer, but finds underlayers of PE-SiH₄ or TEOS-N₂ O to beadequate without plasma treatment.

SUMMARY OF THE INVENTION

Accordingly, it is a primary object of the invention to provide aprocess for improving the gap filling characteristics of O₃ -TEOS inshallow trench isolation in the fabrication of integrated circuits.

It is a further object of the invention to provide a process forimproving the step coverage of ozone-TEOS in shallow trench isolation.

It is yet another object to provide a process for improving the stepcoverage of ozone-TEOS by forming a PE-OX underlayer with N₂ treatmentfor shallow trench isolation.

It is a still further object of the invention to provide a process forimproving step coverage of ozone-TEOS for shallow trench isolation byforming an underlayer wherein the surface of the underlayer maintainssmoothness.

In accordance with the objects of the invention, an improved method ofgap filling shallow trench isolation with ozone-TEOS is achieved. A padoxide layer is provided over the surface of a semiconductor substrate. Anitride layer is deposited overlying the pad oxide layer. A plurality ofisolation trenches is etched through the nitride and pad oxide layersinto the semiconductor substrate. A thermal oxide layer is grown withinthe isolation trenches. A plasma enhanced SiH₄ oxide layer is depositedover the nitride layer and over the thermal oxide layer within theisolation trenches and treated with N₂ plasma. Thereafter, an ozone-TEOSlayer is deposited overlying the plasma enhanced SiH₄ oxide layer andfilling the isolation trenches. The ozone-TEOS layer and the plasmaenhanced SiH₄ oxide layer are polished away stopping at the nitridelayer. This completes the formation of shallow trench isolation in thefabrication of the integrated circuit device.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of thisdescription, there is shown:

FIGS. 1-8 are cross-sectional representations of a preferred embodimentof the present invention.

FIG. 9 is a cross-sectional representation of a shallow isolation trenchof the prior art.

FIG. 10 is a cross-sectional representation of a completed integratedcircuit device fabricated according to the process of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now more particularly to FIG. 1, there is shown asemiconductor substrate 10, preferably of monocrystalline silicon.Shallow trench isolation regions are to be formed in the semiconductorsubstrate to isolate active areas of the integrated circuit device fromone another. A layer of pad oxide 12 is grown on the surface of thesubstrate. A layer of silicon nitride 14 is deposited over the pad oxidelayer.

Referring now to FIG. 2, shallow trenches are etched into the siliconsubstrate using conventional photolithography and etching techniques.The shallow trenches 16 may be as small as 0.35 microns in width and areetched to a depth of between about 3000 and 5000 Angstroms.

A thermal oxide layer 17 is grown on the sidewalls of the trench 16 to athickness of about 350 Angstroms, as depicted in FIG. 3. This thermaloxide provides a good sidewall isolation.

Now the trenches are to be filled with a dielectric material. Thetrenches will be filled with ozone-TEOS. First, an underlayer is to bedeposited within the trenches to eliminate surface sensitivity and toeliminate the deleterious effects of the thermal oxide underlayer on O₃-TEOS deposition and wet etch rates.

In the paper by Kwok et al, cited above, the authors find that anunderlayer of PE-SiH₄ oxide does not adversely effect deposition or wetetch rates of the overlying O₃ -TEOS layer for gap filling of metallines. However, the inventors of the present invention have found thateven a PE-SiH₄ oxide underlayer causes problems for the shallow trenchisolation application.

We have tried various plasma-enhanced chemical vapor deposited (PECVD)oxides followed by plasma treatment to form the underlayer. We havefound that the best results occur when PE-SiH₄ is deposited togetherwith an N₂ plasma treatment.

Referring to FIG. 4, a layer of plasma-enhanced silane oxide SiH₄ 18 isdeposited by plasma enhanced chemical vapor deposition (PECVD) over thesurface of the substrate and within the trenches 16. This layer will bereferred to henceforth as the PE-OX underlayer. The PE-OX underlayer isdeposited to a thickness of between about 350 and 600 Angstroms. Thesidewall and bottom step coverage of the PE-OX is between about 20% to30%.

After the PE-OX deposition, the N₂ plasma treatment 20 is performed, asshown in FIG. 5. N₂ gas is flowed at between about 400 to 600 sccm andHelium is flowed at between 1800 to 2200 sccm at a pressure of betweenabout 1 to 2 Torr for between about 50 to 70 seconds. It is expectedthat Argon gas could be used in place of the nitrogen gas with similareffect.

Referring now to FIG. 6, a layer of O₃ -TEOS 22 is deposited overlyingthe PE-OX underlayer. The ozone-TEOS layer 22 is deposited overlying thePE-OX layer 18 by subatmospheric chemical vapor deposition to athickness of between about 5000 and 7000 Angstroms. The bottom andsidewall step coverage of the O₃ -TEOS layer will be 100%. Theozone-TEOS layer also has some flow characteristics. No voids are formedwithin the layer 22 because of the complete gap filling.

The process of the invention results in voidless gap filling ofozone-TEOS in the shallow isolation trenches down to 0.35 microns inwidth. A great improvement in surface morphology is also seen.

Referring now to FIG. 7, the ozone-TEOS layer 22 and the PE-OX layer 18above the level of the trenches are removed, for example, by chemicalmechanical polishing (CMP).

The silicon nitride is etched away and the pad oxide is removed usingwet etching or dipping. These wet dips and pre-gate oxide cleaning canattack the ozone-TEOS surface. In some approaches, porosity appears inthe ozone-TEOS surface. However, in the process of the presentinvention, the surface is still smooth after these steps. This completesthe formation of the shallow trench isolation, as illustrated in FIG. 8.

Semiconductor device structures, including gate electrodes 32 and sourceand drain regions 34 may be formed as is conventional in the art.Electrical contacts 38 may be made through dielectric isolation layer36, as shown in FIG. 10.

EXAMPLE

The following Example is given to show the important features of theinvention and to aid the understanding thereof. Variations may be madeby one skilled in the art without departing from the spirit and scope ofthe invention.

Experiments were performed to fill a STI trench using SACVD O₃ -TEOS. Insample 1, there was no underlayer. The O₃ -TEOS was deposited directlyoverlying the thermal oxide layer. In sample 2, the thermal oxide layerwas treated with N₂ plasma for one minute, then O₃ -TEOS was deposited.In the remaining samples 3-7, various underlayers were deposited overthe thermal oxide layer before the deposition of O₃ -TEOS. The followingtable details the underlayers tested and shows the results of theexperiments. Trench bulk refers to the gap filling quality of the O₃-TEOS filling after all wet dips have been performed (that is, wet dipsto remove the silicon nitride and pad oxide and to clean the surface).

                  TABLE 1                                                         ______________________________________                                        Sample Underlayer or treatment                                                                       Trench bulk                                                                             Trench sidewall                              ______________________________________                                        1      None            No dep    severe porosity                              2      N.sub.2 treatment 1 min.                                                                      seamless  severe porosity                              3      1000A 60 Torr O.sub.3 -TEOS                                                                   seamless  clean but recess                             4      500-1500A PE-OX voiding   clean                                        5      500-1500A DEL-TEOS +                                                                          seamless  severe porosity                                     N.sub.2 treatment 1 min.                                               6      500-1500A PE-TEOS +                                                                           seamless  severe porosity                                     N.sub.2 treatment 1 min.                                               7      500-1500A PE-OX +                                                                             seamless  little porosity                                     N.sub.2 treatment 1 min.                                               ______________________________________                                    

The experiments included conventional furnace densification after the O₃-TEOS deposition to improve the quality of the O₃ -TEOS film. Forsamples 2 and 3, the furnace densification was performed at 1000° C. for30 minutes. For samples 4-7, the densification was performed at1000°-1100° C. for two hours.

It can be seen from the table above that a seamless gap filling of thetrench was achieved in all the methods accept the first sample in whicha negligible amount of O₃ -TEOS was deposited because of the very lowdeposition rate over thermal oxide and the fourth sample in whichvoiding occurred. Note that the fourth sample uses an underlayer ofPE-OX, which is the PE-SiH₄ underlayer of the present invention butwithout the N₂ treatment.

Samples 5-7 used a nitrogen treatment of the underlayers. Sample 5 hadan underlayer of dual-frequency TEOS, sample 6 had an underlayer ofPE-TEOS, and sample 7 had a underlayer of PE-OX; that is, the PE-SiH₄underlayer of the present invention.

FIG. 9 illustrates the sample 3 after polishing and wet dips. The trenchis filled without voids. However, the O₃ -TEOS underlayer 21 has a highwet etch rate. This causes recessing 25 of the underlayer duringpolishing and wet dips to complete the STI which exposes the silicon andmay cause a leakage problem.

Only in sample 7, using the process of the present invention, wasseamless gap filling along with little sidewall porosity achieved.

For shallow trench isolation, good gap filling is not the only criterionfor choosing an underlayer for O₃ -TEOS. The underlayer must also beable to withstand the polishing, wet etching, and wet dipping performedto complete the shallow trench isolation and to prepare the surface forthe formation of gate electrodes and other devices. The process of thepresent invention uses an underlayer of PE-SiH₄ treated with N₂ plasmato provide for seamless gap filling and a smooth surface for shallowtrench isolation.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

What is claimed is:
 1. A method of manufacturing an integrated circuitdevice comprising:providing a pad oxide layer over the surface of asemiconductor substrate; depositing a nitride layer overlying said padoxide layer; etching a plurality of isolation trenches through saidnitride and said pad oxide layers into said semiconductor substrate;depositing a plasma enhanced SiH₄ oxide layer over said nitride layerand within said isolation trenches and treating said plasma enhancedSiH₄ oxide layer with N₂ plasma; thereafter depositing an ozone-TEOSlayer overlying said plasma enhanced SiH₄ oxide layer and filling saidisolation trenches; polishing away said ozone-TEOS layer and said plasmaenhanced SiH₄ oxide layer stopping at said silicon nitride layer; andcompleting the fabrication of said integrated circuit device.
 2. Themethod according to claim 1 further comprising growing a thermal oxidelayer within said isolation trenches before said depositing of saidplasma enhanced SiH₄ oxide layer.
 3. The method according to claim 2wherein said thermal oxide layer has a thickness of about 350 Angstroms.4. The method according to claim 1 wherein said plasma enhanced SiH₄oxide layer is deposited to a thickness of between about 350 and 600Angstroms.
 5. The method according to claim 1 wherein said N₂ plasmatreatment comprises flowing N₂ gas at 400 to 600 sccm and flowing heliumat 1800 to 2200 sccm at a pressure of 1 to 2 Torr for 50 to 70 seconds.6. The method according to claim 1 wherein said width of said isolationtrenches is as small as 0.35 microns.
 7. The method according to claim 1wherein said polishing is done by chemical mechanical polishing.
 8. Themethod according to claim 1 wherein said isolation trenches arecompletely filled with said ozone-TEOS layer and wherein no voids areformed within said ozone-TEOS layer.
 9. The method according to claim 1wherein said completing fabrication of said integrated circuit devicecomprises:etching away said silicon nitride layer; removing said padoxide layer; and fabricating semiconductor device structures in and onsaid semiconductor substrate between said isolation trenches.
 10. Amethod of forming shallow trench isolation in the manufacture anintegrated circuit device comprising:providing a pad oxide layer overthe surface of a semiconductor substrate; depositing a nitride layeroverlying said pad oxide layer; etching a plurality of isolationtrenches through said nitride and said pad oxide layers into saidsemiconductor substrate; depositing a plasma enhanced SiH₄ oxide layerover said nitride layer and within said isolation trenches and treatingsaid plasma enhanced SiH₄ oxide layer with N₂ plasma; thereafterdepositing an ozone-TEOS layer overlying said plasma enhanced SiH₄ oxidelayer and filling said isolation trenches; polishing away saidozone-TEOS layer and said plasma enhanced SiH₄ oxide layer stopping atsaid silicon nitride layer; etching away said nitride layer; andremoving said pad oxide layer to complete said formation of said shallowtrench isolation in the fabrication of said integrated circuit device.11. The method according to claim 10 further comprising growing athermal oxide layer within said isolation trenches before saiddepositing of said plasma enhanced SiH₄ oxide layer.
 12. The methodaccording to claim 11 wherein said thermal oxide layer has a thicknessof about 350 Angstroms.
 13. The method according to claim 10 whereinsaid plasma enhanced SiH₄ oxide layer is deposited to a thickness ofbetween about 350 and 600 Angstroms.
 14. The method according to claim10 wherein said N₂ plasma treatment comprises flowing N₂ gas at 400 to600 sccm and flowing helium at 1800 to 2200 sccm at a pressure of 1 to 2Torr for 50 to 70 seconds.
 15. The method according to claim 10 whereinsaid width of said isolation trenches is as small as 0.35 microns. 16.The method according to claim 10 wherein said polishing is done bychemical mechanical polishing.
 17. The method according to claim 10wherein said isolation trenches are completely filled with saidozone-TEOS layer and wherein no voids are formed within said ozone-TEOSlayer.
 18. The method according to claim 10 wherein said completedshallow trench isolation has a smooth surface.
 19. A method ofmanufacturing an integrated circuit device comprising:providing a padoxide layer over the surface of a semiconductor substrate; depositing anitride layer overlying said pad oxide layer; etching a plurality ofisolation trenches through said nitride and said pad oxide layers intosaid semiconductor substrate; growing a thermal oxide layer within saidisolation trenches; depositing a plasma enhanced SiH₄ oxide layeroverlying said nitride layer and overlying said thermal oxide layerwithin said isolation trenches and treating said plasma enhanced SiH₄oxide layer with N₂ plasma; thereafter depositing an ozone-TEOS layeroverlying said plasma enhanced SiH₄ oxide layer and filling saidisolation trenches; polishing away said ozone-TEOS layer and said plasmaenhanced SiH₄ oxide layer stopping at said silicon nitride layer;etching away said nitride layer; removing said pad oxide layer; andcompleting the fabrication of said integrated circuit device.
 20. Themethod according to claim 19 wherein said N₂ plasma treatment comprisesflowing N₂ gas at 400 to 600 sccm and flowing helium at 1800 to 2200sccm at a pressure of 1 to 2 Torr for 50 to 70 seconds.
 21. The methodaccording to claim 19 wherein said width of said isolation trenches isas small as 0.35 microns.
 22. The method according to claim 19 whereinsaid isolation trenches are completely filled with said ozone-TEOS layerand wherein no voids are formed within said ozone-TEOS layer.
 23. Themethod according to claim 19 wherein said completing fabrication of saidintegrated circuit device comprises fabricating semiconductor devicestructures including gate electrodes and source and drain regions andelectrical connections between said device structures in and on saidsemiconductor substrate between said isolation trenches.